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ADuC7060

COMPLETE MMR LISTING

In the following MMR tables, addresses are listed in hexadecimal code. Access types include R for read, W for write, and R/W for read

and write.

Table 16. IRQ Address Base = 0xFFFF0000

Access

Default

Address

0x0000

0x0004

0x0008

0x000C

0x0010

0x0014

Name

IRQSTA

IRQSIG

IRQEN

IRQCLR

SWICFG

IRQBASE

Byte

4

4

4

4

4

4

Type

R

R

R/W

W

W

R/W

Value

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Description

Active IRQ source.

Current state of all IRQ sources (enabled and disabled).

Enabled IRQ sources.

MMR to disable IRQ sources.

Software interrupt configuration MMR.

Base address of all vectors. Points to the start of the 64-byte memory block,

which can contain up to 32 pointers to separate subroutine handlers.

0x001C

IRQVEC

4

R

0x00000000

This register contains the subroutine address for the currently active IRQ

source.

0x0020

IRQP0

4

R/W

0x00000000

Contains the interrupt priority setting for interrupt Source 1 to Source 7.

An interrupt can have a priority setting of 0 to 7. For example:

Bits[7:4] contain the priority level for Interrupt 1.

Bits[11:8] contain the priority level for Interrupt 2.

Bits[31:28] contain the priority level for Interrupt 7.

0x0024

IRQP1

4

R/W

0x00000000

Contains the interrupt priority setting for Interrupt Source 8 to Interrupt

Source 15. For example:

Bits[7:4] contain the priority level for Interrupt 9.

Bits[11:8] contain the priority level for Interrupt 10.

Bits[31:28] contain the priority level for Interrupt 15.

0x0028

IRQP2

4

R/W

0x00000000

Contains the interrupt priority setting for Interrupt Source 16 to Interrupt

Source 19.

0x0030

0x0034

IRQCONN

IRQCONE

4

4

R/W

R/W

0x00000000

0x00000000

Used to enable IRQ and FIQ interrupt nesting.

Configures the external interrupt sources as rising edge, falling edge, or

level triggered.

0x0038

0x003C

IRQCLRE

IRQSTAN

4

4

R/W

R/W

0x00000000

0x00000000

Used to clear an edge-level-triggered interrupt source.

This register indicates the priority level of an interrupt that has just

caused an interrupt exception.

0x0100

0x0104

0x0108

0x010C

0x011C

0x013C

FIQSTA

FIQSIG

FIQEN

FIQCLR

FIQVEC

FIQSTAN

4

4

4

4

4

4

R

R

R/W

W

R

R/W

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Active FIQ source.

Current state of all FIQ sources (enabled and disabled).

Enabled FIQ sources.

MMR to disable FIQ sources.

FIQ interrupt vector.

Indicates the priority level of an FIQ that has just caused an FIQ

exception.

Table 17. System Control Address Base = 0xFFFF0200

Access

Address

0x0220

0x0230

0x0234

Name

REMAP 1

RSTSTA

RSTCLR

Byte

1

1

1

Type

R/W

R/W

W

Default Value

0x00

0x01

0x00

Description

REMAP control register. See the Remap Operation section.

RSTSTA status MMR. See the Reset section.

RSTCLR MMR for clearing the RSTSTA register.

1

Updated by the kernel.

Rev. 0 | Page 24 of 100

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